The present invention relates to a semiconductor memory device and a method for fabricating the same, and more particularly to a semiconductor memory device equipped with a capacitor having a large capacitance and a method for fabricating the same.
With the development of semiconductor devices, researches have been actively made for integrating a large number of elements on a single semiconductor chip in a high integration degree. In particular, various cell structures have been proposed for obtaining a minimum dimension in memory cells of dynamic random access memories (DRAMs).
In terms of the minimized dimension for the high integration, each memory cell is desired to be constituted by one transistor and one capacitor. In such a memory cell constituted by one transistor and one capacitor, a signal charge is stored in a storage node of the capacitor connected to a transistor (switching transistor). As the dimension of the memory cell is reduced with an increase in integration degree of the semiconductor memory device, the dimension of the capacitor is reduced, thereby causing the number of signal charges stored in the storage node to be reduced. For transmitting a desired signal without any malfunction, accordingly, the capacitor storage node of the memory cell should have a surface area larger than a predetermined value for obtaining a capacitance of the capacitor required for the signal transmission.
For achieving a reduction in memory cell dimension, the storage node of the capacitor should have a relatively large surface area in a limited region defined on a semiconductor substrate.
There have been proposed various methods for increasing the surface area of the capacitor storage node.
One of methods for increasing the surface area of the capacitor storage node and thus maximizing the capacitance of the capacitor is to fabricate a capacitor having a three-dimensional structure. Up to the present, there have been proposed a variety of three-dimensional structures such as a fin structure, a cylinder structure and a box structure.
Among the three-dimensional structures, the cylinder structure is the structure capable of obtaining a maximum capacitance per unit area. Accordingly, the cylinder structure can be applicable to memory devices of DRAMs of a 16 mega-bit grade or greater.
Now, a method for fabricating a conventional cylinder type capacitor will be described, in conjunction with FIGS. 1a to 1g.
In accordance with the method, a field oxide film 2 is formed on a semiconductor substrate 1 so as to define an active region and an element isolation region in the semiconductor substrate 1, as shown in FIG. 1a. Thereafter, a cell transistor constituted by a gate electrode 3 and source and drain region S/D is formed on a semiconductor substrate 1 by use of a general MOS transistor fabrication process. An insulating layer 4 is formed over the entire exposed surface of the resulting structure and then selectively etched to form a contact hole through which the source region or the drain region of the cell transistor is exposed.
As shown in FIG. 1b, a first polysilicon layer 5 is formed to a thickness of 1,500 to 2,000 .ANG. over the entire exposed surface of the resulting structure. Over the first polysilicon layer 5, an oxide film 6 is formed to a thickness of 5,000 to 6,000 .ANG.. Then, a photoresist pattern 7 is formed on the oxide film 6 by use of a photolithography process using a mask for forming a capacitor storage node.
Using the photoresist pattern 7 as a mask, the oxide film 6 and the first polysilicon layer 5 are etched to form a storage node pattern, as shown in FIG. 1c.
Subsequently, the photoresist pattern 7 is removed, as shown in FIG. 1d. After the removal of the photoresist pattern 7, a second polysilicon layer 8 is formed over the entire exposed surface of the resulting structure. As shown in FIG. 1e, the second polysilicon layer 8 is etched back to form side walls 8A comprised of the second polysilicon layer 8 on the side surfaces of the oxide film 6 and the first polysilicon layer 5.
Thereafter, the oxide film 6 is removed, as shown in FIG. 1f. As a result, a capacitor storage node having a cylinder structure is formed which is constituted by the first polysilicon layer 5 and the second polysilicon side walls 8A.
A capacitor dielectric film 9 is then formed over the entire exposed surface of the resulting structure, as shown in FIG. 1g. Finally, a conduction material is deposited over the capacitor dielectric film 9, thereby forming a capacitor plate electrode 10. Thus, a cylinder type capacitor is fabricated.
In terms of the occupied area of the capacitor storage node, however, this conventional cylinder type capacitor has a drawback of a degraded efficiency of a three-dimensional space utilization because it has a cylindrical structure (the side wall portions denoted by the reference numeral 9 in FIG. 1g) at the outer portion of the storage node pattern while a space is defined in the interior of the cylindrical structure.